Contributors
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Designer, IP and Embedded Systems Track Poster Networking Reception Root-cause analysis of undefined slack using timing/netlist data model
A
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
Designer, IP and Embedded Systems Track Poster Networking Reception Verification Methodology for High Resolution High Speed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED End-to-End Solution for structured implementation of high-speed data buses
Research Manuscript Architecture-aware Precision Tuning with Multiple Number Representation Systems*
Designer, IP and Embedded Systems Track Poster Networking Reception Optimizing hold eco using ML techniques
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Poster Networking Reception Memory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction
Designer, IP and Embedded Systems Track Poster Networking Reception New file system to automatically "spill" workloads across Datacenter and Cloud
Networking Reception Parameter Approximation in CNNs for Improved Inference on FPGA
Designer, IP and Embedded Systems Track Poster Networking Reception Power Management Verification of AMD Radeon RX 5000 and RX 6000 Series GPUs
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Designer, IP and Embedded Systems Track Presentations Verifying Reset and Power Domains Together
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Research Manuscript Deep Integration of Circuit Simulator and SAT Solver
Research Manuscript LUT-Based Optimization For ASIC Design Flow
Designer, IP and Embedded Systems Track Presentations Aging aware Static Timing Analysis
Designer, IP and Embedded Systems Track Presentations Thermal-aware SOC floorplanning method based on a customized Deep-Q Network algorithm
Research Manuscript Control Variate Approximation for DNN Accelerators
Research Manuscript Max-PIM: Fast and Efficient Max/Min Searching in DRAM
Research Manuscript PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Research Manuscript Smarter Software Frameworks for Easier ML Development
Research Manuscript AID: Attesting the Integrity of Deep Neural Networks
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Presentations UVM is 10 Years Old: What's Next?
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
Research Manuscript Falcon Down: Breaking the Falcon Post-Quantum Signature Scheme through Side-Channel Attacks
Research Manuscript Security Techniques across the Board (STAB)
Research Manuscript An Approximate World from Neurons to Genomes
B
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Late Breaking Results Poster Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification
DAC Pavilion Panels Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Designer, IP and Embedded Systems Track Poster Networking Reception Andes ACE feature extended on Menta eFPGA for RISC-V cores ISA reconfigurability in the field
Designer, IP and Embedded Systems Track Poster Networking Reception Embedded Security optimized with eFPGA
Designer, IP and Embedded Systems Track Poster Networking Reception Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio
Research Manuscript SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping
Designer, IP and Embedded Systems Track Presentations High Bandwidth All-Digital Clock and Data Recovery Architecture
Designer, IP and Embedded Systems Track Presentations Exchanging EDA data for AI/ML using Standard API
Designer, IP and Embedded Systems Track Poster Networking Reception Extended Power Connectivity Solution for CPF based Low Power Simulation
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Designer, IP and Embedded Systems Track Presentations Deep data for faster silicon bring-up, characterization, and qualification with higher confidence
Research Manuscript Optimized Polynomial Multiplier Architectures forPost-Quantum KEM Saber
Research Manuscript SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED End-to-End Solution for structured implementation of high-speed data buses
Designer, IP and Embedded Systems Track Poster Networking Reception Predicting Timing Bottlenecks in Place & Route using Machine Learning
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Special Session (Research Track) Accelerating PCB Layout Editor using modern GPU architecture for complex designs
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Designer, IP and Embedded Systems Track Poster Networking Reception Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow
Designer, IP and Embedded Systems Track Presentations Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator
Designer, IP and Embedded Systems Track Poster Networking Reception Early Layout Area and PLS Estimation by Designers
Designer, IP and Embedded Systems Track Presentations Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation
Designer, IP and Embedded Systems Track Presentations Mitigating Variability Challenges of IPs for Robust Design
Designer, IP and Embedded Systems Track Presentations Verifying Reset and Power Domains Together
Special Session (Research Track) Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Research Manuscript Property-driven Automatic Generation of Reduced-ISA Hardware
Belgium
Special Session (Research Track) Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems
Research Manuscript A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms
Research Manuscript RoboRun: A Robot Runtime to Exploit Spatial Heterogeneity
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
France
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Special Session (Research Track) tinyML on embedded microprocessors and the broad avenue of opportunities
Research Manuscript Deep Integration of Circuit Simulator and SAT Solver
Designer, IP and Embedded Systems Track Presentations UVM is 10 Years Old: What's Next?
Networking Reception A Robust DNN Accelerator with Data-path Fault Detection and Mitigation
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
C
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Research Manuscript On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage
Research Manuscript PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Designer, IP and Embedded Systems Track Presentations What can chip design learn from the software world?
China
Research Manuscript HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
Research Manuscript Enabling the Design of Behavioral Systems-on-Chip
Designer, IP and Embedded Systems Track Presentations Monica - On-chip Monitoring Systems Characterization
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Research Manuscript Architecture-aware Precision Tuning with Multiple Number Representation Systems*
Designer, IP and Embedded Systems Track Presentations Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Research Manuscript Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Designer, IP and Embedded Systems Track Presentations Performance Modeling of Digital Processing Systems
Designer, IP and Embedded Systems Track Poster Networking Reception An Automated Approach to Pre-empt Clock-Divergence & Achieve Predictable Timing Closure
Designer, IP and Embedded Systems Track Presentations New Frontiers in Formal and Static Verification
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
Research Manuscript Obfuscated Priority Assignment to CAN-FD Messages with Dependencies: A Swapping-based and Affix-Matching Approach
Research Manuscript A Bridge-based Compression Algorithm for Topological Quantum Circuits
Research Manuscript Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
Research Manuscript Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Germany
Designer, IP and Embedded Systems Track Presentations Power Minimization of MCM/2.5D Chip-2-Chip communication interface
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Research Manuscript Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators
Research Manuscript Efficient Tunstall Decoders for Compressed Deep Neural Network
Special Session (Research Track) kCC-Net for Compression of Biomedical Image Segmentation Networks
Research Manuscript Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
China
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Late Breaking Results Poster Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning
Research Manuscript Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
Research Manuscript AID: Attesting the Integrity of Deep Neural Networks
Networking Reception SimpleChisel: A Hardware Design Language for Component-Level Heterogeneous Designs
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
China
Research Manuscript An Intelligent Video Processing Architecture for Edge-cloud Video Streaming
Research Manuscript LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM
China
Research Manuscript Efficient Tunstall Decoders for Compressed Deep Neural Network
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Research Manuscript Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
Research Manuscript A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Research Manuscript Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Research Manuscript A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Research Manuscript A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Research Manuscript Architecture-aware Precision Tuning with Multiple Number Representation Systems*
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Research Manuscript Architecture-aware Precision Tuning with Multiple Number Representation Systems*
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Research Manuscript Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations Machine Learning Based Efficient Regression Test Framework in SOC Verification
Research Manuscript A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States
Designer, IP and Embedded Systems Track Presentations Efficient Data Exchange Towards Faster Functional Safety Development
Networking Reception RTL regression test selection using Machine Learning
Research Manuscript Local Bayesian Optimization for Analog Circuit Sizing
Networking Reception Efficient Real-Time Object Detection with Adaptive Image Scaling and Cropping
Networking Reception POSAR: A Flexible Posit Arithmetic Unit for RISC-V
Research Manuscript On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage
Designer, IP and Embedded Systems Track Presentations Exchanging EDA data for AI/ML using Standard API
Designer, IP and Embedded Systems Track Poster Networking Reception Early Layout Area and PLS Estimation by Designers
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
D
Designer, IP and Embedded Systems Track Presentations Comprehensive processor security verification: A CIA problem
Designer, IP and Embedded Systems Track Presentations Deep data for faster silicon bring-up, characterization, and qualification with higher confidence
Research Manuscript Automating Autonomy: From GPU to Traffic Control
Research Manuscript Reliability from Fab to Mission
Google Senior Fellow and SVP for Google Research and Google Health
Research Manuscript SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
Research Manuscript New Predictor-Based Attacks in Processors
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Designer, IP and Embedded Systems Track Poster Networking Reception Optimizing hold eco using ML techniques
Designer, IP and Embedded Systems Track Poster Networking Reception Formal Verification of Safety Mechanisms | Infineon Technologies
Research Manuscript ISA Modeling with Trace Notation for Context Free Property Generation
Designer, IP and Embedded Systems Track Poster Networking Reception On the Energy Efficiency of Machine Learning Frameworks
Designer, IP and Embedded Systems Track Presentations Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator
Designer, IP and Embedded Systems Track Presentations Solidifying your SOC beyond Design
Designer, IP and Embedded Systems Track Presentations Monica - On-chip Monitoring Systems Characterization
Special Session (Research Track) Security Primitives with Emerging Memories
Designer, IP and Embedded Systems Track Poster Networking Reception Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Designer, IP and Embedded Systems Track Poster Networking Reception MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Research Manuscript Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: A Information-Theoretic Approach
Special Session (Research Track) Progress and Challenges of 3D Vision & Deep Learning in Industrial Robotics Application
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Research Manuscript SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
Research Manuscript Classifying Computations on Multi-Tenant FPGAs
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations Scoring Vectors for IR Sign-off Using Power-Weighted Coverage Metrics
E
Designer, IP and Embedded Systems Track Presentations ECO patch generation & stitching to facilitate concurrent ECOs in High Performance Processor Designs
Research Manuscript Secure Logic Locking with Strain-Protected Nanomagnet Logic
Designer, IP and Embedded Systems Track Presentations A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs
Designer, IP and Embedded Systems Track Presentations “Debug in/on/with the Virtual Platform” – Please Clarify!
Designer, IP and Embedded Systems Track Poster Networking Reception Efficient High-Sigma Verification of Standard Cell Libraries
Networking Reception RTL regression test selection using Machine Learning
Research Manuscript Deep Learn your Yield
Research Manuscript Learn to Design better NoC
F
Designer, IP and Embedded Systems Track Presentations Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
Research Manuscript PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Research Manuscript Max-PIM: Fast and Efficient Max/Min Searching in DRAM
Research Manuscript PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Research Manuscript In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic Processor
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Research Manuscript A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
Research Manuscript Approximate Equivalence Checking of Noisy Quantum Circuits
Research Manuscript SGL: Spectral Graph Learning from Measurements
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Research Manuscript High-Performance FPGA-based Accelerator for Bayesian Neural Networks
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Designer, IP and Embedded Systems Track Presentations UVM is 10 Years Old: What's Next?
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Designer, IP and Embedded Systems Track Presentations Clocking Methods with Focus on PCIe Gen4
Designer, IP and Embedded Systems Track Presentations All Routes Lead to Closing Timing
Research Manuscript Architecture-aware Precision Tuning with Multiple Number Representation Systems*
Special Session (Research Track) Safety in Autonomous Driving: Can Tools Offer Guarantees?
Designer, IP and Embedded Systems Track Poster Networking Reception Machine learning Assisted Design Rule Debug and Rule Ranking Automation
Designer, IP and Embedded Systems Track Presentations Towards measuring layout pattern coverage: a Machine Learning Approach
Designer, IP and Embedded Systems Track Presentations Accelerating mutation coverage measurement by using concurrent fault simulator
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
G
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
China
Research Manuscript An Intelligent Video Processing Architecture for Edge-cloud Video Streaming
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript Interactive Analog Layout Editing with Instant Placement Legalization
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: A Single Solution for Scanning, Tracking Inventory, Transactions, and Recharging
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Fast Tracking a Federal Authentication Solution for Secure Facilities
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Designer, IP and Embedded Systems Track Presentations Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Hold Buffer Insertion
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Research Manuscript An Efficient Algorithm for Sparse Quantum State Preparation
Research Manuscript Classifying Computations on Multi-Tenant FPGAs
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Networking Reception Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Special Session (Research Track) Always-On modules demonstrate that tinyML is already here!
Research Manuscript MyML: User-Driven Machine Learning
Designer, IP and Embedded Systems Track Presentations Innovative Techniques to Accelerate Error Handling Verification of Complex Systems
Research Manuscript OpenMem: Hardware/Software Cooperative Management for Mobile Memory System
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Modernizing Public Infrastructure with Interactive Devices
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Designer, IP and Embedded Systems Track Poster Networking Reception Embedded Security optimized with eFPGA
Designer, IP and Embedded Systems Track Presentations Smart digital sensors against tampering
Research Manuscript Critical Design for Timing Critical Systems
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Special Session (Research Track) Integration of IC Design Changes into a BlockChain for Traceability in AISS Design Flow
Research Manuscript SPACE: Security of Post-Quantum and Accelerator-based Cryptographic Engines
Special Session (Research Track) Security-Aware Computer Aided Electronic Design
Special Session (Research Track) Vision of Automating the Implementation of Security into Silicon
Networking Reception RTL regression test selection using Machine Learning
Research Manuscript GPU-accelerated Path-based Timing Analysis
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Research Manuscript HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
H
Designer, IP and Embedded Systems Track Poster Networking Reception MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Modernizing a Nationwide Indoor/Outdoor Package Sorting System
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Rethinking New Product Introduction to Better Align to Client Needs
Networking Reception Context-Aware Task Handling in Resource-Constrained Robots with Virtualization
Designer, IP and Embedded Systems Track Presentations Getting started on Cloud Playbook
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
Designer, IP and Embedded Systems Track Presentations Aging aware Static Timing Analysis
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
China
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Research Manuscript Secure Logic Locking with Strain-Protected Nanomagnet Logic
Research Manuscript Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
China
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
China
Research Manuscript TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Networking Reception EdgenAI: Distributed Inference with Local Edge Devices and Minimum Latency
Research Manuscript Fast, Cool and Error Tolerant Compute-In-Memory
Research Manuscript Intelligent Software and System Architectures for Smart Memories
Research Manuscript Novel Strategies for I/O Systems and Devices Management
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems
Research Manuscript RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System
Research Manuscript TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers
Research Manuscript An Efficient Algorithm for Sparse Quantum State Preparation
Research Manuscript DANCE: Differentiable Accelerator/Network Co-Exploration
Research Manuscript Approximate Equivalence Checking of Noisy Quantum Circuits
Networking Reception Novel Static Timing Analysis considering Dynamic Voltage Drop
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Research Manuscript A Bridge-based Compression Algorithm for Topological Quantum Circuits
Designer, IP and Embedded Systems Track Presentations SoC Architectural Exploration for AI and ML accelerators with RISC-V
Research Manuscript Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial Networks
Research Manuscript Enabling On-Device Self-supervised Contrastive Learning With Selective Data Contrast
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Singapore
Research Manuscript ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs
Research Manuscript GPU-accelerated Path-based Timing Analysis
Late Breaking Results Poster Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints
Research Manuscript Classifying Computations on Multi-Tenant FPGAs
Designer, IP and Embedded Systems Track Poster Networking Reception Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools
Research Manuscript Theory-Specific Proof Steps Witnessing Correctness of SMT Executions
I
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Presentations Accelerating mutation coverage measurement by using concurrent fault simulator
Research Manuscript CascadeHD: Efficient Many-Class Learning Framework Using Hyperdimensional Computing
Research Manuscript Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional System
Research Manuscript PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems
Research Manuscript RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
J
Designer, IP and Embedded Systems Track Poster Networking Reception Optimizing Fault Simulations with Formal Analysis for Asil Compliance
Research Manuscript DIALED: Data Integrity Attestation for Low-end Embedded Devices
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
Research Manuscript RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Research Manuscript Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation
Research Manuscript HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
Research Manuscript TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
Research Manuscript Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation
Research Manuscript Deep Integration of Circuit Simulator and SAT Solver
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Special Session (Research Track) Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment
Research Manuscript Smarter Compute Engines for Greener ML
China
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
Research Manuscript HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing
Research Manuscript PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
Research Manuscript HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing
Research Manuscript Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
Designer, IP and Embedded Systems Track Presentations Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
Research Manuscript A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Designer, IP and Embedded Systems Track Presentations WOW: Approximate WOrkload Watcher
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Designer, IP and Embedded Systems Track Presentations What can chip design learn from the software world?
Designer, IP and Embedded Systems Track Poster Networking Reception Cloud Infrastructure for Remote and Scalable EDA Hardware Training
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
DAC Pavilion Panels Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
Research Manuscript From Brains to Bits
Research Manuscript Intelligent Edge-Cloud Computing Architectures for CPS
Designer, IP and Embedded Systems Track Presentations A flexible SAR-ADC IP for multiple technodes
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
K
Networking Reception A Coordinated GPU Overdrive Fault Attack on Neural Networks
Designer, IP and Embedded Systems Track Presentations Exchanging EDA data for AI/ML using Standard API
Designer, IP and Embedded Systems Track Presentations Methodology for Accurate Analysis of Dynamic Voltage Drop Induced Clock Jitter for Improved PPA
Designer, IP and Embedded Systems Track Presentations Enhanced Analytics and Reporting for Triage and Sign-off Timing
Designer, IP and Embedded Systems Track Presentations Exchanging EDA data for AI/ML using Standard API
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript When They Go High - We Go Low (in Computation)
Designer, IP and Embedded Systems Track Presentations Optimal Function Clock Aware Scan Methodology
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Research Manuscript GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection
Designer, IP and Embedded Systems Track Presentations Strategy for Mixed Signal IP Integration to Accelerate High-Quality SOC Development
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Research Manuscript Classifying Computations on Multi-Tenant FPGAs
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation
Designer, IP and Embedded Systems Track Poster Networking Reception Constraints based CDC Sign-Off methodology
Networking Reception Towards Deploying PSS to Early Design Space Exploration
Designer, IP and Embedded Systems Track Presentations Mitigating Variability Challenges of IPs for Robust Design
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Professor of the Graduate School in EECS
Networking Reception CoDR: Computation and Data Reuse Aware CNN Accelerator
Special Session (Research Track) Accelerating PCB Layout Editor using modern GPU architecture for complex designs
Special Session (Research Track) Mask Synthesis in the Era of GPU Computing and Deep Learning
Special Session (Research Track) NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Machine Learning Based Efficient Regression Test Framework in SOC Verification
Designer, IP and Embedded Systems Track Presentations On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis
Research Manuscript Dynamic Chip Clustering and Task Allocation for Real-time Flash
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Designer, IP and Embedded Systems Track Presentations Accurate glitch noise analysis considering impact of secondary aggressors
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Designer, IP and Embedded Systems Track Presentations Machine Learning Based Efficient Regression Test Framework in SOC Verification
Designer, IP and Embedded Systems Track Poster Networking Reception MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Networking Reception SpecMCTS: Accelerating Monte Carlo Tree Search using Speculative Tree Traversal
Networking Reception HammerFilter: Robust Protection and Low Hardware Overhead Method for Row-Hammering
Designer, IP and Embedded Systems Track Poster Networking Reception MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception PI Signoff Methods Used in a 5nm InFO Design
Designer, IP and Embedded Systems Track Poster Networking Reception Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Estimation
Designer, IP and Embedded Systems Track Presentations WOW: Approximate WOrkload Watcher
Designer, IP and Embedded Systems Track Presentations Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
Designer, IP and Embedded Systems Track Poster Networking Reception MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
Designer, IP and Embedded Systems Track Presentations WOW: Approximate WOrkload Watcher
Designer, IP and Embedded Systems Track Presentations Virtual Environment for Developing Reinforcement Learning and Its application for thermal management
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Networking Reception Guiding Global Placement with Reinforcement Learning
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Belgium
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Presentations Algorithm to RTL: A Faster Path to Implementation
Designer, IP and Embedded Systems Track Poster Networking Reception A Spring Model Approach For Timing Budget Apportionment
Designer, IP and Embedded Systems Track Presentations Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
Research Manuscript A-Eye on the Cutting Edge of IoT
Research Manuscript Keep Your Secrets Safe: Side-channel Attacks and Assessment techniques
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Designer, IP and Embedded Systems Track Presentations Embedded Systems! Projects and Solutions
Designer, IP and Embedded Systems Track Presentations Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States
Special Session (Research Track) Accelerating PCB Layout Editor using modern GPU architecture for complex designs
Designer, IP and Embedded Systems Track Presentations Overlapping Checkers – A Better Substitute of End-to-End Checkers
Designer, IP and Embedded Systems Track Poster Networking Reception Multi-core System Verification Using Uvm Portable Stimulus
Designer, IP and Embedded Systems Track Poster Networking Reception Optimizing Fault Simulations with Formal Analysis for Asil Compliance
Designer, IP and Embedded Systems Track Poster Networking Reception Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow
Designer, IP and Embedded Systems Track Presentations Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation
Designer, IP and Embedded Systems Track Presentations Machine Learning based IR Drop Prediction on ECO Revised Designs for Faster Convergence
Research Manuscript A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Research Manuscript Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Designer, IP and Embedded Systems Track Poster Networking Reception Accelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
L
Designer, IP and Embedded Systems Track Presentations Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation
Designer, IP and Embedded Systems Track Presentations Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
Designer, IP and Embedded Systems Track Poster Networking Reception RISC-V processor verification methodology with dynamic testbench for asynchronous events
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Research Manuscript SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
Research Manuscript Statheros: Compiler for Efficient Low-Precision Probabilistic Programming
Networking Reception ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Hybrid Emulation Methodology for SSD Design
Research Manuscript Noise-Robust Deep Spiking Neural Networks with Temporal Information
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Networking Reception Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
Research Manuscript Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
DARPA Program Manager, Microsystems Technology Office (MTO)
TechTalk Reimagining Digital Simulation
Special Session (Research Track) Vision of Automating the Implementation of Security into Silicon
Research Manuscript A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator
Hong Kong
Research Manuscript MobileSwap: Cross-Device Memory Swapping for Mobile Devices
Research Manuscript SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
China
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams
Research Manuscript TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
Designer, IP and Embedded Systems Track Presentations Power Minimization for peak power and improved GPU sustainability
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
China
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Research Manuscript Approximate Equivalence Checking of Noisy Quantum Circuits
Research Manuscript From Brains to Bits
Research Manuscript That Quantum Session Everyone Is Talking About
Research Manuscript SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
China
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams
Research Manuscript TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
Research Manuscript A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Late Breaking Results Poster Physical Adversarial Attacks of Diffractive Deep Neural Networks
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
Research Manuscript HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
China
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Research Manuscript TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
Research Manuscript A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Designer, IP and Embedded Systems Track Presentations Scoring Vectors for IR Sign-off Using Power-Weighted Coverage Metrics
Research Manuscript Efficient Tunstall Decoders for Compressed Deep Neural Network
Designer, IP and Embedded Systems Track Poster Networking Reception Multi-Physics Simulation Techniques toward Electromagnetic Side-Channel Attack Assessments on IC Chip Assembly
Research Manuscript A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Research Manuscript A Bridge-based Compression Algorithm for Topological Quantum Circuits
Research Manuscript A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs
Research Manuscript GPU-accelerated Path-based Timing Analysis
Research Manuscript Ultrafast CPU/GPU Kernels for Density Accumulation in Placement
Research Manuscript Let There Be Light: Emerging Technology for Intelligent Systems
Research Manuscript Evolved Neural-Hardware-Compiler Co-Design
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Designer, IP and Embedded Systems Track Presentations Efficient Data Exchange Towards Faster Functional Safety Development
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Networking Reception DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism
Research Manuscript New Trends in Memory Architecture Designs for I/O Systems
China
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization
Research Manuscript TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
Research Manuscript ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Designer, IP and Embedded Systems Track Presentations PUF-based HRoT for Supply Chain Security
Research Manuscript Interactive Analog Layout Editing with Instant Placement Legalization
Special Session (Research Track) Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities
Singapore
Research Manuscript ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Research Manuscript HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
China
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Research Manuscript PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Networking Reception POSAR: A Flexible Posit Arithmetic Unit for RISC-V
Designer, IP and Embedded Systems Track Poster Networking Reception Early Layout Area and PLS Estimation by Designers
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Research Manuscript Synergically Rebalancing Parallel Execution via DCT and Turbo Boosting
Special Session (Research Track) Quantum Random Access Coding in Quantum Machine Learning Applications
Research Manuscript TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
Research Manuscript A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms
Research Manuscript PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
Research Manuscript TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
M
Research Manuscript HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Designer, IP and Embedded Systems Track Presentations Novel end to end Non-coherent access mechanism on X86 SOC
Designer, IP and Embedded Systems Track Presentations Getting started on Cloud Playbook
Designer, IP and Embedded Systems Track Presentations Getting started on Cloud Playbook
Designer, IP and Embedded Systems Track Presentations Systematic Generation and Refresh of Standard Cell Abutment Database
Research Manuscript Ultrafast CPU/GPU Kernels for Density Accumulation in Placement
Designer, IP and Embedded Systems Track Presentations What can chip design learn from the software world?
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation
Research Manuscript Beyond Supervised Learning: Approaches for Efficient and Reliable Intelligence
Research Manuscript Reinforced: Analog Circuit Sizing and Layout
Research Manuscript LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM
Late Breaking Results Poster Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement
Designer, IP and Embedded Systems Track Presentations Enhanced Hyperscaling of Data Centers using In-Chip Monitoring & Sensing Fabrics
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Stress Testing to Survive an Industrial Gas Turbine
Research Manuscript Speculations on Routes to Boost Power and Energy Efficiency
Designer, IP and Embedded Systems Track Poster Networking Reception AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Research Manuscript In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic Processor
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Research Manuscript SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Research Manuscript SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Networking Reception A High Efficiency Power Obfuscation Switched Capacitor DC-DC Converter Architecture
Designer, IP and Embedded Systems Track Poster Networking Reception Accurate and efficient high-performance memory modeling for full-chip power noise analysis
Research Manuscript Deep Integration of Circuit Simulator and SAT Solver
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Special Session (Research Track) kCC-Net for Compression of Biomedical Image Segmentation Networks
Networking Reception Procrastinating CFI for Hard Real-Time Systems
Designer, IP and Embedded Systems Track Presentations What can chip design learn from the software world?
Designer, IP and Embedded Systems Track Poster Networking Reception Novel Chip-Package-System Power Noise Analysis with RTL Power Profiling
Designer, IP and Embedded Systems Track Poster Networking Reception SHIFT LEFT: NOVEL POWER ANALYSIS METHOD for LARGE-SCALE AI PROCESSORS
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Presentations Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States
Designer, IP and Embedded Systems Track Presentations Exchanging EDA data for AI/ML using Standard API
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Designer, IP and Embedded Systems Track Presentations Shift-left Post-Silicon verification with Speed and Accuracy
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
Designer, IP and Embedded Systems Track Presentations Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation
Research Manuscript Reconfigurability across the Spectrum: From ICs to Intelligence
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Presentations Verifying Reset and Power Domains Together
Designer, IP and Embedded Systems Track Presentations Novel end to end Non-coherent access mechanism on X86 SOC
Designer, IP and Embedded Systems Track Presentations Novel end to end Non-coherent access mechanism on X86 SOC
Special Session (Research Track) The Current State of TinyML – Opportunities, Challenges and the Road Ahead
Research Manuscript HLock: Locking IPs at the High-Level Language
N
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Senior Vice President, Corporate Fellow, and Product Technology Architect United States of America
Designer, IP and Embedded Systems Track Presentations A Low Cost, Scalable and Predictable Gate Level Simulation Methodology for Giga-Scale SOCs
Designer, IP and Embedded Systems Track Presentations Get more out of your UVM register Layer!
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
Designer, IP and Embedded Systems Track Poster Networking Reception Efficient High-Sigma Verification of Standard Cell Libraries
Networking Reception RTL regression test selection using Machine Learning
Designer, IP and Embedded Systems Track Poster Networking Reception AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Special Session (Research Track) CIRCT - Circuit IR Compilers and Tools
Networking Reception ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM
Designer, IP and Embedded Systems Track Presentations Is Your Product Secure? - An IP Driven Approach to Product Security
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations Machine Learning based IR Drop Prediction on ECO Revised Designs for Faster Convergence
Designer, IP and Embedded Systems Track Presentations An automated decision-making tool to accelerate Computational SRAM design for memory-bound applications
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
O
Networking Reception CANCELLED: IO Performance Modeling for Communication Workloads
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Designer, IP and Embedded Systems Track Presentations Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
Designer, IP and Embedded Systems Track Presentations Chip Design and Cloud: the Good, the Emerging, and the Potential
DAC Pavilion Panels Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Designer, IP and Embedded Systems Track Presentations WOW: Approximate WOrkload Watcher
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Research Manuscript AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Designer, IP and Embedded Systems Track Presentations IP Enabling the Intended Function. The Unloved IP.
Designer, IP and Embedded Systems Track Presentations Accelerating mutation coverage measurement by using concurrent fault simulator
P
Late Breaking Results Poster Late Breaking Results: Parallelizing Net Routing with cGANs
Research Manuscript Designing a 2048-Chiplet, 14336-Core Waferscale Processor
Research Manuscript Learning to Accelerate Circuit Timing Analysis
Special Session (Research Track) Accelerating EDA Algorithms with GPUs and Machine Learning
Special Session (Research Track) Accelerating PCB Layout Editor using modern GPU architecture for complex designs
Research Manuscript Deep Learn your Yield
Special Session (Research Track) Mask Synthesis in the Era of GPU Computing and Deep Learning
Special Session (Research Track) NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Research Manuscript Beyond Supervised Learning: Approaches for Efficient and Reliable Intelligence
Designer, IP and Embedded Systems Track Presentations Enabling Hierarchical Flattened Functional ECO Flow for Quality Patch Generation with Runtime Benefits
Special Session (Research Track) Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Research Manuscript Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: A Information-Theoretic Approach
Special Session (Research Track) Mastering the three pillars of accelerator design for Deep Learning
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Research Manuscript Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning
Research Manuscript SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
Designer, IP and Embedded Systems Track Presentations Innovative Techniques to Accelerate Error Handling Verification of Complex Systems
Designer, IP and Embedded Systems Track Poster Networking Reception Efficient Impedance Discontinuity Optimization Technique for High Speed Interfaces
Research Manuscript A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Research Manuscript Noise-Robust Deep Spiking Neural Networks with Temporal Information
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Research Manuscript Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Networking Reception RTL regression test selection using Machine Learning
Designer, IP and Embedded Systems Track Presentations Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Research Manuscript A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms
Research Manuscript Transforming Emerging Technologies in the Post-Moore Era
Special Session (Research Track) Mask Synthesis in the Era of GPU Computing and Deep Learning
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Special Session (Research Track) Requirement Specification, Analysis and Verification for Autonomous Systems
Designer, IP and Embedded Systems Track Presentations Monica - On-chip Monitoring Systems Characterization
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Designer, IP and Embedded Systems Track Presentations Machine Learning based IR Drop Prediction on ECO Revised Designs for Faster Convergence
Designer, IP and Embedded Systems Track Poster Networking Reception New file system to automatically "spill" workloads across Datacenter and Cloud
Designer, IP and Embedded Systems Track Presentations A flexible SAR-ADC IP for multiple technodes
Designer, IP and Embedded Systems Track Poster Networking Reception Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio
DAC Pavilion Panels Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Poster Networking Reception Ensuring Completeness of Formal Verification with GapFree: Are we done yet?
Special Session (Research Track) Quantum Random Access Coding in Quantum Machine Learning Applications
Q
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Research Manuscript A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Networking Reception DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism
Research Manuscript In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic Processor
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
Research Manuscript AID: Attesting the Integrity of Deep Neural Networks
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
R
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED End-to-End Solution for structured implementation of high-speed data buses
Research Manuscript SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
Networking Reception RTL regression test selection using Machine Learning
Designer, IP and Embedded Systems Track Presentations Innovative Techniques to Accelerate Error Handling Verification of Complex Systems
DAC Pavilion Panels Handling SoC Verification: Changing the Paradigm in Verification Approaches
Special Session (Research Track) Accelerating Fully Homomorphic Encryption with Processing in Memory
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Special Session (Research Track) More Than Moore But More Secure? On the Security Challenges and Opportunities of Emerging Technologies
Research Manuscript SHIPP - Security Hardening for Intellectual Property Protection
Special Session (Research Track) Security Primitives with Emerging Memories
Designer, IP and Embedded Systems Track Presentations Methodology for early timing and floorplanning closure in custom circuit design
Networking Reception POSAR: A Flexible Posit Arithmetic Unit for RISC-V
Special Session (Research Track) Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems
Designer, IP and Embedded Systems Track Presentations Systematic Generation and Refresh of Standard Cell Abutment Database
Research Manuscript SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
Special Session (Research Track) The Current State of TinyML – Opportunities, Challenges and the Road Ahead
Designer, IP and Embedded Systems Track Poster Networking Reception Priority Synthesis in Physical Synthesis
Designer, IP and Embedded Systems Track Presentations Routing layer re-optimization in Physical Synthesis
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Designer, IP and Embedded Systems Track Presentations Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
Designer, IP and Embedded Systems Track Presentations A flexible SAR-ADC IP for multiple technodes
Special Session (Research Track) NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Research Manuscript SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Research Manuscript Classifying Computations on Multi-Tenant FPGAs
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Designer, IP and Embedded Systems Track Presentations Christmas Lights Displays As Embedded Systems
VP Machine Learning Group
TechTalk The AI hype cycle is over. Now what?
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Research Manuscript Smarter Software Frameworks for Easier ML Development
Special Session (Research Track) Accelerating Fully Homomorphic Encryption with Processing in Memory
Research Manuscript Locks, Clones and Hammers: Trusting your chip in a vulnerable world
Research Manuscript On the Intrinsic Robustness of NVM Crossbars against Adversarial Attacks
Networking Reception RTL regression test selection using Machine Learning
S
Networking Reception CANCELLED: SonicFFT: A system architecture for ultrasonic-based FFT acceleration
Research Manuscript Efficient Tunstall Decoders for Compressed Deep Neural Network
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Designer, IP and Embedded Systems Track Presentations Algorithm to RTL: A Faster Path to Implementation
Research Manuscript KV-SSD: What is it Good For?
Designer, IP and Embedded Systems Track Presentations Accelerating mutation coverage measurement by using concurrent fault simulator
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Designer, IP and Embedded Systems Track Presentations UVM is 10 Years Old: What's Next?
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Special Session (Research Track) Safety in Autonomous Driving: Can Tools Offer Guarantees?
Designer, IP and Embedded Systems Track Poster Networking Reception MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Networking Reception Learning Quantum Circuit Errors Based on Error Propagation
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Special Session (Research Track) Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Executive Vice President
Belgium
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Designer, IP and Embedded Systems Track Poster Networking Reception Extended Power Connectivity Solution for CPF based Low Power Simulation
Designer, IP and Embedded Systems Track Presentations Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Designer, IP and Embedded Systems Track Presentations Analog Fault Simulation for Automotive Sensor Designs
Designer, IP and Embedded Systems Track Presentations Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Special Session (Research Track) Safety in Autonomous Driving: Can Tools Offer Guarantees?
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Research Manuscript SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM
Research Manuscript SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments
Special Session (Research Track) The Current State of TinyML – Opportunities, Challenges and the Road Ahead
Special Session (Research Track) tinyML – tiny in size, BIG in impact!
Research Manuscript Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning
Designer, IP and Embedded Systems Track Presentations Performance Modeling of Digital Processing Systems
Special Session (Research Track) Progress and Challenges of 3D Vision & Deep Learning in Industrial Robotics Application
Designer, IP and Embedded Systems Track Presentations PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow
Designer, IP and Embedded Systems Track Presentations Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator
Research Manuscript Enabling the Design of Behavioral Systems-on-Chip
Designer, IP and Embedded Systems Track Presentations Aging Timing Analysis Based on EMPYREAN-XTime
China
Research Manuscript MobileSwap: Cross-Device Memory Swapping for Mobile Devices
Research Manuscript Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices
Research Manuscript Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial Networks
Research Manuscript Enabling On-Device Self-supervised Contrastive Learning With Selective Data Contrast
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Designer, IP and Embedded Systems Track Presentations Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Designer, IP and Embedded Systems Track Presentations Middle of Layer Routing Enablement for Increasing Routing Resource
Designer, IP and Embedded Systems Track Presentations Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Research Manuscript Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Designer, IP and Embedded Systems Track Presentations Power Minimization for peak power and improved GPU sustainability
Research Manuscript Transforming Emerging Technologies in the Post-Moore Era
Special Session (Research Track) Mastering the three pillars of accelerator design for Deep Learning
Research Manuscript Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding
Designer, IP and Embedded Systems Track Poster Networking Reception Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow
Designer, IP and Embedded Systems Track Presentations High Bandwidth All-Digital Clock and Data Recovery Architecture
Research Manuscript Optimized Polynomial Multiplier Architectures forPost-Quantum KEM Saber
Designer, IP and Embedded Systems Track Poster Networking Reception New file system to automatically "spill" workloads across Datacenter and Cloud
Designer, IP and Embedded Systems Track Presentations A comprehensive UPF coverage methodology to avoid late Si Issues
Designer, IP and Embedded Systems Track Presentations Abstraction- An efficient methodology for RTL & Low-Power Signoff in SoC Design
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Networking Reception Determining the Multiplicative Complexity of Boolean Functions using SAT
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
China
Designer, IP and Embedded Systems Track Presentations Novel end to end Non-coherent access mechanism on X86 SOC
Research Manuscript Local Bayesian Optimization for Analog Circuit Sizing
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Designer, IP and Embedded Systems Track Presentations UVM is 10 Years Old: What's Next?
Designer, IP and Embedded Systems Track Presentations Efficient System PDN Analysis Methodat Pre-Layout Stage
Designer, IP and Embedded Systems Track Presentations Verifying Reset and Power Domains Together
Research Manuscript A Melange of Machine Learning Frameworks for Optimization
Research Manuscript AIVengers: Emerging AI Algorithms to the Rescue
Designer, IP and Embedded Systems Track Poster Networking Reception Pioneering Low Power Modeling and Verification Technique for custom blocks
Designer, IP and Embedded Systems Track Presentations Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
DAC Pavilion Panels Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Research Manuscript GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks
Research Manuscript Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
Designer, IP and Embedded Systems Track Presentations UVM: Where the Wild Things Are
United States of America
Research Manuscript ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
China
Research Manuscript CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator
Designer, IP and Embedded Systems Track Poster Networking Reception Fast and Accurate DvD aware Timing Analysis
Designer, IP and Embedded Systems Track Poster Networking Reception Early Layout Area and PLS Estimation by Designers
Research Manuscript New Predictor-Based Attacks in Processors
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
T
Designer, IP and Embedded Systems Track Presentations Enhanced Analytics and Reporting for Triage and Sign-off Timing
Designer, IP and Embedded Systems Track Poster Networking Reception A Highly Reusable Generic UVM for Soft Processors
Designer, IP and Embedded Systems Track Presentations PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow
Special Session (Research Track) Functional Criticality Classification of Structural Faults in AI Accelerators
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Singapore
Research Manuscript Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
Designer, IP and Embedded Systems Track Poster Networking Reception Accelerating Standard Cells Variation-Aware Characterization Methodology with Machine Learning Techniques
Designer, IP and Embedded Systems Track Poster Networking Reception Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Special Session (Research Track) Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Networking Reception POSAR: A Flexible Posit Arithmetic Unit for RISC-V
Research Manuscript Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
Special Session (Research Track) End-to-End Secure SoC Lifecycle Management
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Networking Reception POSAR: A Flexible Posit Arithmetic Unit for RISC-V
Special Session (Research Track) Always-On modules demonstrate that tinyML is already here!
Special Session (Research Track) The Current State of TinyML – Opportunities, Challenges and the Road Ahead
Special Session (Research Track) tinyML – tiny in size, BIG in impact!
Special Session (Research Track) tinyML on embedded microprocessors and the broad avenue of opportunities
Designer, IP and Embedded Systems Track Presentations Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation
Special Session (Research Track) Quantum Random Access Coding in Quantum Machine Learning Applications
Networking Reception DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism
Designer, IP and Embedded Systems Track Presentations A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs
Research Manuscript Local Bayesian Optimization for Analog Circuit Sizing
Designer, IP and Embedded Systems Track Presentations Tune in to the Clocks!
Designer, IP and Embedded Systems Track Presentations Optimal Function Clock Aware Scan Methodology
Research Manuscript Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation
Research Manuscript A Bridge-based Compression Algorithm for Topological Quantum Circuits
Special Session (Research Track) Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Special Session (Research Track) CIRCT - Circuit IR Compilers and Tools
Special Session (Research Track) Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED End-to-End Solution for structured implementation of high-speed data buses
U
Designer, IP and Embedded Systems Track Presentations MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Late Breaking Results Poster Late Breaking Results: Parallelizing Net Routing with cGANs
V
Special Session (Research Track) Integration of IC Design Changes into a BlockChain for Traceability in AISS Design Flow
Designer, IP and Embedded Systems Track Presentations Monica - On-chip Monitoring Systems Characterization
Designer, IP and Embedded Systems Track Presentations Strategy for Mixed Signal IP Integration to Accelerate High-Quality SOC Development
Special Session (Research Track) Security Primitives with Emerging Memories
Designer, IP and Embedded Systems Track Poster Networking Reception Verification Methodology for High Resolution High Speed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools
Research Manuscript Quantum Spectral Clustering of Mixed Graphs
W
Designer, IP and Embedded Systems Track Poster Networking Reception CANCELLED: Beyond Lint
Research Manuscript Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems
Research Manuscript A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Research Manuscript Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
Designer, IP and Embedded Systems Track Poster Networking Reception "OpenOPU" , A Complete Solution for Heterogeneous Computing
Research Manuscript LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM
Designer, IP and Embedded Systems Track Presentations Power Minimization for peak power and improved GPU sustainability
Research Manuscript LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM
China
Research Manuscript ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator
Research Manuscript An Intelligent Video Processing Architecture for Edge-cloud Video Streaming
Research Manuscript GCiM: A Near-Data Processing Accelerator for Graph Construction
Research Manuscript Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization
Research Manuscript PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams
Research Manuscript TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
China
Research Manuscript PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams
Special Session (Research Track) Progress and Challenges of 3D Vision & Deep Learning in Industrial Robotics Application
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Designer, IP and Embedded Systems Track Poster Networking Reception "OpenOPU" , A Complete Solution for Heterogeneous Computing
Research Manuscript Efficient Tunstall Decoders for Compressed Deep Neural Network
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Research Manuscript SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture
Research Manuscript OpenMem: Hardware/Software Cooperative Management for Mobile Memory System
Designer, IP and Embedded Systems Track Presentations Power Minimization for peak power and improved GPU sustainability
Special Session (Research Track) Building scalable variational circuit training for machine learning tasks
Special Session (Research Track) Drug Discovery Approaches using Quantum Machine Learning
Special Session (Research Track) Quantum Random Access Coding in Quantum Machine Learning Applications
DAC Pavilion Panels How System Companies are Re-shaping requirements for EDA
Research Manuscript GPU-accelerated Path-based Timing Analysis
Research Manuscript Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
Research Manuscript New Regular Expressions on Old Accelerators
Research Manuscript An Automated and Process-Portable Generator for Phase-Locked Loop
Designer, IP and Embedded Systems Track Poster Networking Reception RISC-V processor verification methodology with dynamic testbench for asynchronous events
Research Manuscript Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Designer, IP and Embedded Systems Track Presentations PUF-based HRoT for Supply Chain Security
X
Research Manuscript SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture
Research Manuscript SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Research Manuscript MobileSwap: Cross-Device Memory Swapping for Mobile Devices
Y
Designer, IP and Embedded Systems Track Presentations PUF-based HRoT for Supply Chain Security
Research Manuscript Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation
Designer, IP and Embedded Systems Track Presentations A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Research Manuscript Verification is running: what are the next stops?
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Special Session (Research Track) Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment
Special Session (Research Track) kCC-Net for Compression of Biomedical Image Segmentation Networks
Research Manuscript A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Designer, IP and Embedded Systems Track Presentations BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
Designer, IP and Embedded Systems Track Presentations DIMM Level Verification Methodology for DRAM Custom DFT
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Designer, IP and Embedded Systems Track Presentations Architectural Formal Sign-Off of Compression System Data Coherency
Research Manuscript GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection
Designer, IP and Embedded Systems Track Presentations How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Designer, IP and Embedded Systems Track Presentations Get more out of your UVM register Layer!
Designer, IP and Embedded Systems Track Poster Networking Reception Analog in memory computing optimization with TOPS/W Methodology
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript Approximate Equivalence Checking of Noisy Quantum Circuits
Designer, IP and Embedded Systems Track Poster Networking Reception An Automated Approach to Pre-empt Clock-Divergence & Achieve Predictable Timing Closure
Designer, IP and Embedded Systems Track Poster Networking Reception Optimizing hold eco using ML techniques
Research Manuscript Noise-Robust Deep Spiking Neural Networks with Temporal Information
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Special Session (Research Track) Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities
Late Breaking Results Poster Physical Adversarial Attacks of Diffractive Deep Neural Networks
Research Manuscript Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning
Research Manuscript PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
Research Manuscript GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Z
Designer, IP and Embedded Systems Track Presentations What can chip design learn from the software world?
Designer, IP and Embedded Systems Track Presentations PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow
Special Session (Research Track) MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices
Research Manuscript Enabling On-Device Self-supervised Contrastive Learning With Selective Data Contrast
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Research Manuscript A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
Research Manuscript Towards Resilient Deployment of In-Memory Neural Networks with High Throughput
Research Manuscript PRUID: Practical User Interface Distribution for Multi-surface Computing
Research Manuscript ROLoad: Securing Sensitive Operations with Pointee Integrity
Research Manuscript Max-PIM: Fast and Efficient Max/Min Searching in DRAM
Research Manuscript PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript Deep Integration of Circuit Simulator and SAT Solver
Research Manuscript ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Research Manuscript ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator
Research Manuscript An Intelligent Video Processing Architecture for Edge-cloud Video Streaming
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Research Manuscript PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation
Research Manuscript A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
Research Manuscript PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Networking Reception DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism
Research Manuscript F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding
Research Manuscript Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation
China
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Research Manuscript MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Research Manuscript BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Research Manuscript A Lightweight Isolation Mechanism for Secure Branch Predictors
Research Manuscript Neural Pruning Search for Real-Time Object Detection of Autonomous Vehicles
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
Research Manuscript SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Research Manuscript PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Research Manuscript SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Research Manuscript JPDHeap: A JVM Heap Design for PM-DRAM Memories
Special Session (Research Track) TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin
Research Manuscript MAT: Processing In-Memory Acceleration for Long-Sequence Attention
Research Manuscript Fantastic SoCs and Where to Find Them!
Research Manuscript A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
Research Manuscript Approximate Equivalence Checking of Noisy Quantum Circuits
Research Manuscript Quantifying Rowhammer Vulnerability for DRAM Security
Special Session (Research Track) Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
Special Session (Research Track) Requirement Specification, Analysis and Verification for Autonomous Systems
Special Session (Research Track) Safety in Autonomous Driving: Can Tools Offer Guarantees?
Special Session (Research Track) Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities
Research Manuscript HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
Special Session (Research Track) Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Research Manuscript Bayesian Inference Based Robust Computing on Memristor Crossbar
Research Manuscript RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System
Late Breaking Results Poster Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement
Research Manuscript PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
China
Research Manuscript SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Research Manuscript A Resource Binding Approach to Logic Obfuscation*
Special Session (Research Track) Independent Verification and Validation of Security-Aware EDA Tools and IP