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Organization

Synopsys
Session Chair(s)
Khader Abdel-Hafez
Ramsay Allen
Tareq Altakrouri
Luca Amaru
Mike Borza
Mike Borza
Christopher Casares
Wenwen Chai
Boon-Siang Cheah
Shivakumar Chonnad
Parivesh Choudhary
Adam Cron
Stephen Crosher
Li Ding
Malan Evans
Randy Fish
Hansika Gunasekara
Ruifeng Guo
Tae-Jin Jung
Neeraj Kaul
Vishal Khandelwal
YongJoon Kim
Venkataraghavan Krishnan
Vladimir Litovtchenko
Yi-Chen Lu
Jiong Luo
Felipe Marranghello
Hillel Miller
Saleem Mohammad
Saurav Nanda
Siddhartha Nath
Sashi Obilisetty
Sashi Obilisetty
Sridhar Panchapakes
Sungjin Park
Ganapathy Parthasarathy
Girish Patankar
Vinicius Possani
Jiri Prevratil
Sridhar Rajakumar
Aabid Rushdi
Kwangsoo Seo
Rakesh Panemangalore Shenoy
James P. Shiely
Eleonora Testa
Patrick Vuillod
Session Chairs
Maheshwar Chandrasekar
Jovanka Ciric Vujkovic
Renu Mehra
Sashi Obilisetty
Murthy Palla
Presentations
Designer, IP and Embedded Systems Track Presentations
Analog Fault Simulation for Automotive Sensor Designs
Front-End Design
Hosted in Virtual Platform
Research Manuscript
Deep Integration of Circuit Simulator and SAT Solver
EDA
RTL/Logic Level and High-level Synthesis
Hosted in Virtual Platform
TechTalk
Delivering Systemic Innovation to Power the Era of SysMoore
Hosted in Virtual Platform
Presented In-Person
DAC Pavilion Panels
Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States
Front-End Design
Hosted in Virtual Platform
Designer, IP and Embedded Systems Track Presentations
Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator
IP
Hosted in Virtual Platform
Designer, IP and Embedded Systems Track Presentations
Efficient Data Exchange Towards Faster Functional Safety Development
Front-End Design
Hosted in Virtual Platform
Special Session (Research Track)
End-to-End Secure SoC Lifecycle Management
Security
Hosted in Virtual Platform
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Enhanced Hyperscaling of Data Centers using In-Chip Monitoring & Sensing Fabrics
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Getting started on Cloud Playbook
Cloud
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
How AI and Cloud enable a virtuous cycle in silicon design and manufacturing
Cloud
Machine Learning/AI
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
IP
Security
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
IP Enabling the Intended Function. The Unloved IP.
IP
Presented In-Person
Research Manuscript
LUT-Based Optimization For ASIC Design Flow
EDA
RTL/Logic Level and High-level Synthesis
Presented In-Person
Designer, IP and Embedded Systems Track Poster Networking Reception
Optimizing Fault Simulations with Formal Analysis for Asil Compliance
Presented In-Person
Tutorial
Practical Application of AI/ML to EDA Problems
EDA
Machine Learning/AI
Presented In-Person
Research Manuscript
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
EDA
Digital Design, Timing and Simulation
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation
Presented In-Person
Networking Reception
Work-in-Progress Poster
RTL regression test selection using Machine Learning
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
Back-End Design
Hosted in Virtual Platform
Research Manuscript
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
EDA
RTL/Logic Level and High-level Synthesis
Presented In-Person
Research Manuscript
Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval
EDA
Physical Design and Verification, Lithography and DFM
Hosted in Virtual Platform
DAC Pavilion Panels
Trust and verify. Overcoming costly and piecemeal approaches to pre-silicon side-channel attack vulnerability analysis and verification
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
UVM: Where the Wild Things Are
Front-End Design
Presented In-Person
Sessions
Designer, IP and Embedded Systems Track Presentations
Chip Design and Cloud: the Good, the Emerging, and the Potential
Cloud
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
New Frontiers in Formal and Static Verification
Front-End Design
Presented In-Person
Research Manuscript
Speculations on Routes to Boost Power and Energy Efficiency
EDA
Cross-Layer Power Analysis and Low-Power Design
Presented In-Person
Research Manuscript
Learning to Accelerate Circuit Timing Analysis
EDA
Digital Design, Timing and Simulation
Presented In-Person
Research Manuscript
Logic Synthesis got even better. Can you believe it? Machine learning to the rescue
EDA
RTL/Logic Level and High-level Synthesis
Presented In-Person