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Organization

Imperas Software Ltd.
Session Chair(s)
Simon Davidmann
Duncan Graham
Katherine (Kat) Hsu
Lee Moore
Presentations
Designer, IP and Embedded Systems Track Poster Networking Reception
RISC-V processor verification methodology with dynamic testbench for asynchronous events
Presented In-Person
Designer, IP and Embedded Systems Track Presentations
SoC Architectural Exploration for AI and ML accelerators with RISC-V
Embedded Systems
Presented In-Person