Innovative Techniques to Accelerate Error Handling Verification of Complex Systems
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionError handling verification is one of the key phases in verification and determining the reliability of any embedded system. It involves verifying that the system correctly detected and gracefully reported various errors. This is especially critical for Smart Network Interface Cards (NICs) (also known as Network Accelerators), as they are usually located in an isolated environment and need to be continuously online with little human interaction. In addition, failure to report an error may result in security vulnerabilities, resulting in a denial of service or other exploits.
Due to the technology advancement in recent years, the complexity of Smart NICs has increased, resulting in a greater number of error scenarios. This has made the task of error handling verification even more challenging using traditional constraint-based random verification.
We leveraged various Formal Property Verification (FPV) techniques including back propagation, design reduction and free variables to address challenges associated with key verification aspects of error handling such as error detection, error reporting and graceful completion. Using these techniques, we completed the error handling verification task for the HW Decompression Accelerator IP six weeks before the schedule and with less than half the number of engineers compared to traditional constraint-based random verification methodology.