CANCELLED End-to-End Solution for structured implementation of high-speed data buses
TimeTuesday, December 7th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionHigh-speed buses require multi-stage pipeline repeater flops to travel large distance (> 10mm) in complex SoCs (size > 200mm2). Meeting stiff performance targets (1Ghz+) on these bidirectional busses across PVT corners is highly challenging. Standard EDA tools do not offer complete solutions and requires user intervention at various stages

This paper proposes an automated solution for structured placement of repeater flops along with a customizable clock tree with minimal user intervention. The solution works in 3 stages:
1. Intelligent placement of pipeline repeater flops, by assessing the distance between ports and direction of data flow.
2. Ladder style clock tree structure provides a skew gradient across repeater flop groups.
3. Buses are trunk routed in a controlled manner to optimize routing resources and crosstalk.
The automation helped in predictable convergence and reducing timing eco cycles.
This solution is independent of technology nodes and is flexible & easily deployable.