Memory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionCustom and manual designs have been mainstream for the memory industry for a long time.
However, as the complexity of the peripheral block has increased, there has been a demand for extending automation methodology to memory designs. However, unlike logic designs, memory designs have distinct characteristics of strong area constraint and harsh P&R environments. To resolve the issues, it is essential to adopt Design Technology Co-Optimization (DTCO) in the early stage.
In this work, we optimize the architecture of standard cells used in peripheral blocks. 1) We apply 4 main items to optimize cell architecture and layout. 2) We estimate the enhancement of P&R feasibility with key P&R factors. 3) We analyze cell performance improvement and corresponding power trade-off with SPICE simulations.
We provide a set of experimental data with 5 representative cells that occupy more than 50% area of the peripheral block. Cell area is reduced to 10%, and propagation delay, rise/fall transition are improved up to 10%. Enhancement of auto P&R feasibility is estimated in terms of 7.6% utilization gain and 5.6% M2 routing track increases.
In future work, we plan to examine actual P&R results and optimize processes in the earlier stage (e.g., design rules).