Presentation
CANCELLED: Beyond Lint
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Presented In-Person
Presenter(s)
DescriptionManagers often see verification as a necessary evil that consumes an outlandish portion of the overall project effort. Any means to reduce the verification effort, therefore, should be grasped with both hands.
Formal consistency checks are one such means. In addition to reducing effort, they can come extremely cheap in terms of engineering hours required. Key here is to provide a framework that enables designers to quickly check their designs before moving to simulation. In addition, a mechanism to create waivers that are not prone to code changes is necessary. Lastly, results must be reported concisely so that any unexpected changes are immediately spotted.
We present a working concept and novel TCL scripting that can be adopted in any Formal tool with TCL support.
Formal consistency checks are one such means. In addition to reducing effort, they can come extremely cheap in terms of engineering hours required. Key here is to provide a framework that enables designers to quickly check their designs before moving to simulation. In addition, a mechanism to create waivers that are not prone to code changes is necessary. Lastly, results must be reported concisely so that any unexpected changes are immediately spotted.
We present a working concept and novel TCL scripting that can be adopted in any Formal tool with TCL support.