Abstraction- An efficient methodology for RTL & Low-Power Signoff in SoC Design
TimeMonday, December 6th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionIn the pursuit of zero Si bug in with predictable schedules, it is extremely important for RTL designers to signoff a good quality RTL to the verification as well as implementation team to ensure that there are minimal ECOs.
For hierarchical SoC, while QoR stub flow or grey box flow comes with accuracy issues, flat has its own challenges with performance and signal to noise (SNR)issues.
Therefore, it becomes mandatory to develop an abstraction methodology for the RTL checking and Low power verification in the SoC design which ensures high quality RTL without any performance impact.
This paper proposes abstraction methodology in the hierarchal SoC design which address issues related to IP-SoC handoff by generating the lint abstract model and static abstraction model and validating the abstract model at the SoC level. In this paper, we would discuss about various advantages and challenges related to Abstraction flow RTL-Lint and RTL-Low power checking in the hierarchical SoC design