Accelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionDeveloping advanced technology nodes entails challenging process ramp up and robust design enablement. A key deterrent for yield ramp-up and EDA design enablement is the lack of quality and comprehensive layout that effectively probe process capabilities and design/process interaction. Process engineers require comprehensive test cases to evaluate process quality, printability and performance. Design Enablement teams require layout to calibrate, develop and QA PDKs that enable SoC engineers to design and validate IC. Guided synthetic layout generation closes the time to resolving these issues. It generates requisite layouts for test-chip development, silicon measurement, process development, PDK development and Design Enablement. It provides comprehensive pattern coverage and stress pattern coverage of the vast design space enabling early problem detection and corrective action to productize robust technology nodes and design enablement flows for SoC designers.

Synthetic layout generation used in advanced testchip development accelerates process ramp up and design enablement. We generate test cases to provide broad coverage of the layout pattern space and directed pattern styles to study stress conditions. Layouts are placed onto test chips for optical and electrical testing. Testchip silicon measurements drive process node maturation. Additional layouts accelerate DRC runset, fill and other PDK development for Design Enablement.