DescriptionCMOS Image Sensor SoCs for cinematography, broadcast, and virtual reality applications require ultra-high resolution (>8K) and high frame rate (>120FPS) needing a column-parallel readout architecture with each column containing more than 10 ADCs and SRAM cells. Verification of such SoCs is extremely challenging due to the sheer size of the extracted post-layout netlist which presents a bottleneck in terms of simulation run time, especially across PVT corners. Another major challenge in verification arises due to the complex mixed-signal system architecture with significant interdependency between analog and digital blocks necessitating a rigorous full-chip functional verification. We present a holistic approach to mitigating these challenges synergizing designer’s knowledge with recent innovations in EDA tools for analog and mixed-signal design and verification to achieve desired Performance, Accuracy, Capacity and Ease-of-Use (PACE). To highlight the benefits of our holistic verification methodology we present two case studies. First, we demonstrate a 3X simulation runtime speedup (with acceptable jitter) using AFS XT as the analog simulator for extracted block-level PLL design. Second, we successfully completed full-chip functional verification for our CMOS Image Sensor SoC using Symphony as the mixed-signal simulator which provided the capacity and flexibility to implement our hierarchical verification methodology.