RISC-V processor verification methodology with dynamic testbench for asynchronous events
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionFor SoC designers adopting RISC-V, tackling the processor DV tasks presents some new
challenges. The established SoC flows have some standard assumptions – test benches written for UVM SystemVerilog flows and known good processor IP from a mainstream supplier. With the availability of open source RISC-V cores and the growing interest to modify or add custom extensions is increasing the DV tasks.
The basic RISC-V compliance suite is insufficient to achieve the coverage requirements for a complete DV test plan, and comparison-based testing with predicted results has built-in limitations. The latest work on dynamic test benches allows the processor RTL to be subjected to the full range of asynchronous events and debug operations. Interactive dynamic test benches allow both detection of issues and also efficient investigation for a timely resolution. This paper will present the latest results from extensively testing some popular open source cores with an open test bench.