DescriptionAccounting for impact of static voltage variations during timing-signoff is a common practice in the industry. Traditionally this is done by adding a voltage margin to ideal supply or adding a timing derate during timing-signoff. These approaches can become very pessimistic, especially for advanced technology nodes having extremely narrow margins. At the same time, there is no consensus in the industry on a methodology that can account for dynamic voltage variations during static timing analysis.
We present a methodology to account for dynamic voltage variations on timing paths using PathFX. PathFX enables a unique methodology to evaluate timing impact on late and early paths. The goal here is to quantify impact of dynamic voltage variations on critical timing paths, with a spice level accuracy, while keeping the results to be bounded as is required for timing-signoff.
We then show how to analyze the most critical and voltage sensitive cells or instances in the design using Seascape technology. These cells can then be used to perform eco, resulting in improved performance robustness to voltage variations.
We demonstrate these through results from a 16nm finfet design.