An Automated Approach to Pre-empt Clock-Divergence & Achieve Predictable Timing Closure
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionSynchronous clock distribution across large hierarchical designs result in huge clock divergence leading to setup-hold critical paths, which are caught late in timing convergence cycle. Early detection of highly divergent clock paths and timely feedback to architecture and design team is crucial in reducing timing iterations.
This paper describes a design-independent automation that can derive all high-risk clock divergent paths at SoC & all subsequent hierarchies downwards, looking at divergent clock path depth and distance.
The script investigates timing paths in the design on a per-clock basis and provides a sorted priority list of critical divergent paths that needs attention. The reports hence generated captures all relevant information useful for clock architects, RTL and physical implementation team. The automation is designed to run on both Primetime & ICC2/Fusion compiler at various design stages such as placement, postCTS and postRoute providing information commensurate to the stage under investigation. The automation can serve as a health check in the early stages to ensure the final timing closure cycle is predictable and smooth.