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Presentation

Optimizing hold eco using ML techniques
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionConventional ECO tools fix hold violations primarily by using cell delays through hold-buffer additions, cell downsizing, Vt swaps. Significant addition of delay cells can lead to congestion. Further cell delays do not scale uniformly across corners and can lead to setup-hold critical paths.

This paper explores an alternate approach for hold-buffer addition, wherein a delay for hold fix is translated to a combination of cell-delay, net-delay, transition, and capacitance values. Window-based filters for measuring congestion are generated around the endpoint wherein the intended buffers will be placed. Our work is based on ML-based real-time filtering of physical data to create a run-set holding the available hold-buffers, fanout, metal-layers, transition, capacitance values, across multiple-corners. Considering non-linearity of the physical aware parameters - SVM, KNN, and Decision Tree classifiers are a few of the approaches involved to provide the best optimal eco. In contrast to contemporary solutions for fixing hold violations, this solution is novel in its approach by involving real-time data for optimizing the required set of physical components by using supervised learning approaches.
Our approach is well scalable and well suited to multiple technology nodes and can be utilized at any level of architectural framework in the physical design domain.