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Presentation

Accurate and efficient high-performance memory modeling for full-chip power noise analysis
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionLong-established methods of analyzing IR drop contribution of power-grid over RAMs utilize RAM models that fall in two categories. (1) Models that provide SPICE level accuracy but require impractical amount of resources to characterize and to analyze large designs. (2) Models that evenly distribute total power/ground current over the RAM, making model generation and analysis much simpler and faster but lack the accuracy needed to perform signoff with high level of confidence. Using any of these methods makes it impossible to simultaneously achieve highly accurate results as well as doing it at the scale required for today’s large semiconductor designs. NVIDIA and ANSYS teamed up to create a new RAM modeling method that allows designers to perform IR drop analysis with accuracy and efficiency that could not be achieved with traditional methods. This new method of modeling RAMs for IR drop takes advantage of the structured layout in RAMs and uniformity of vectors needed to trigger worst-case IR drop to greatly simplify characterization and analysis while maintaining SPICE-like accuracy.