Predicting Timing Bottlenecks in Place & Route using Machine Learning
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionSystem-on-Chip (SoC) design implementation is complex and challenging. The outcome is influenced by lots of variables, ranging from circuit design to process technology. It is a costly and time-consuming process for experienced designers to iterate over multiple floorplans before arriving at one that meets the performance, power and area (PPA) targets. By shortening the time used for floorplan exploration, chip makers can improve Time-To-Market and reduce development cost.

This collaboration between Infineon Technologies and Plunify utilizes Machine Learning to predict the timing bottlenecks in any given floorplan. We leverage domain knowledge and past design data to train a Deep Learning model. Once trained, the model predicts timing bottlenecks in a heatmap format for any input floorplan, allowing designers to make a Go/No-go decision within seconds. If a floorplan is deemed unsuitable, designers can re-work it to resolve the bottlenecks as predicted by the model.