Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionDesign considering variation is required in order to maximize profit and improve PPA because variation impact is increased in the deep-sub micron technilogies The existing POCV method to deal with variation doesn't consider block level timing impact while it applies variation impact on each path. In this study, we propose a methid to analyze and optimize the timing impact due to variation at the block level.