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Presentation

A Low Cost, Scalable and Predictable Gate Level Simulation Methodology for Giga-Scale SOCs
TimeMonday, December 6th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionIncreasing time-to-market pressure with short convergence cycle runway for giga-scale SOCs mandates a GLS methodology that’s cost effective, scalable and predictable. GLS on giga-scale SOCs is costly due to below reasons :-
a. High initial bring-up cost for infrastructure and testbench.
b. Predictability issues with huge monolithic models having capacity and runtime issues.
c. Models with no modular debug hooks.
The ‘Hybrid GLS’ approach with 'Shadow RTL' methodology presented in here addresses these concerns and the results obtained as well as the gains of the approach are shared - as reported from two generations of giga-scale SOC tapeouts. The methodology presented has successfully been applied at IP, Subsystem as well as SOC levels and the qualitative as well as quantitative gains have been presented.