Fast and Accurate DvD aware Timing Analysis
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionOn-chip resistance and cell density are getting increase, especially 7nm technology and below which causes local voltage drop hot-spots that would be occurred dynamically depending on the analysis scenario. Analyzing the impact of dynamic behavior of voltage drop on timing of critical path is required. To be integrated in conventional design flow, the analysis flow requires accuracy and scalability and should be automtaed to smoothly bridge between power and timing domain.