Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
TimeMonday, December 6th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionWe introduce a new design method for routability improvement . It can contributes to save routing resource by using direct pin connection with multiple standard cells with various pin location in advanced node suffered by low layer PDN and more dense metal usage for pin shape. The proposed direct low layer connection focus on reducing routing congestion and detouring for pin routing connection with ① preparing variant pin cells ② enabling P&R method to connect low layer more directly. In this work, we observed that hold fix chain is promising candidate for application and demonstrate variant cell-set targeting for hold fixing are efficient to connect pin more directly without any performance degradation with industrial test-case. In addition, the proposed methods can achieve more than 2% block area scaling using more direct low layer connection. Future work: we are studying for further performance improvement by resistance reduction using low layer direct connection.