Extended Power Connectivity Solution for CPF based Low Power Simulation
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionAdvanced markets drive complex power managed system design with integrated mixed-signal, RF and power management contents. Designs with large number of applications, lowest power consumption and on time delivery are the key contributors in winning the market. powered SoCs require considerably more aggressive power reduction techniques. These require advanced low power (LP) techniques across specification, design, integration, verification and sign-off both custom and semi-custom design contents.
To achieve entitled power with complex and advanced low power design techniques, conventional verification techniques especially those related to power connectivity and functional dependence on power/voltage domain partitions are incapable of delivering required verification quality, coverage and comprehensiveness.
Existing power connectivity solutions include a) custom methods for LP simulation though with significant impact to verification cycle time; b) seamless and fully automated power connection inference for design with underlying power/ground models using real numbered abstractions. They have limitations with power supplies modelled in Boolean/logical abstraction. We present an extended methodology for PA RTL simulation enabling full power connection inference. Several issues were found and fixed during the IP & SoC development phase. Multiple LP AMS SoC designs have used this methodology towards successful tape out and functioning silicon in the hands of end user.