PI Signoff Methods Used in a 5nm InFO Design
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionSuccess in today's electronics market place requires highly integrated chips, at the same time, advanced process nodes create new challenges for integration, different advanced 3DIC (including 2.5D) package structures are proposed.
There are many challenges for 3DIC PI analysis: the modeling of more than 100k frontbumps, the mutual interference between multiple dies and packages, etc. Convergence of these complex circuits requires more effective and reliable PI simulation methods. In this paper, the following analyses are performed based on RedHawk-SC, for a TSMC InFO design.
1.Rapid PI Analysis Technology for InFO
Package and InFO aware chip PI analysis is successfully performed with wrapped model by RedHawk-SC to obtain a accurate simulation of the whole system rapidly.
2.Early-vectorless PI Analysis flow
Early-vectorless PI analysis flow with propagation can be used in early stages, and has higher weakness coverage than VCD flow. Hence, this flow helps to reduce the product time to market.
3.Efficient Method for PI Iteration
An efficient method for PI iteration is proposed. The method can detect all aggressors in a design and their impact, and increase the iteration efficicency finally.