Towards measuring layout pattern coverage: a Machine Learning Approach
TimeMonday, December 6th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionDifferent types of layout pattern are used for yield learning. Despite finding a representative layout pattern is crucial, there is no formal and reliable method to measure the layout pattern coverage. Traditional high dimension reduction techniques such as tSNE, SoM (Self organized map) are used to visualize the pattern space which have the following limitations: 1) process is not reversible. 2) could not measure the coverage numerically. In this paper, we presented a novel method to measure the pattern coverage based on known product pattern space via squish based layout topology representation. The paper covers:
1) Review of traditional high dimension reduction techniques for pattern topology space visualization
2) Autoencoder based ML model for dimension reduction for visualization in discreet latent dimension (using discrete latent dimension vs traditional 2D/3D visualization)
3) A convex Hull (minimum bounding box) in latent dimension method for coverage aggregation
4) Layout pattern generation for yield learning vehicle from space of interest in the latent dimension

ML model architecture and autoencoder training are presented in detail with a focus on techniques on maintain high fidelity of the encoding and decoding process. The methodology is applied in the latest advanced node process development.