Novel Chip-Package-System Power Noise Analysis with RTL Power Profiling
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionWith the evolution of new technologies and new applications, the chip capacity and complexity are constantly increasing. Meanwhile 2.5D and 3D packaging make the design more complex. Package contribution to IR drop (L*di/dt) has become significant for high performance chips. Power noise on package must be considered for power integrity signoff. A compact chip power model (CPM) can be used in spice simulation with package/PCB. However, traditional CPM has only few low frequency components which are dominant on package/PCB. Fast RTL power profiling can generate long-duration power curves that can provide realistic coverage of low frequency components. However, this solution can still hit performance and capacity issues since chip level simulation cannot be completed for designs that are too large and complicated.

We propose a novel flow that runs much faster and easier by constructing a chip level waveform with di/dt sensitive events derived from block level power profiles. ProfilePower runs overnight for our typical large block ~6M gates and ~1GB FSDB of ~800us duration. The power noise simulation result with new CPM is significantly worse at 54mV versus 28mV with original CPM. This correlates better with real chip and underscores importance of this methodology to uncover IR issues.