Hybrid Emulation Methodology for SSD Design
TimeTuesday, December 7th4:30pm - 5:30pm PST
LocationDAC Pavilion
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
DescriptionAs SSD design gets more complicated, faster simulation for HW/FW co-verification is heavily required to improve time-to-market. Hybrid emulation is a viable solution to achieve the requirement by combining a virtual platform with an emulator. In this work, we propose a hybrid emulation methodology considering the characteristics of SSD design which is application-specific and data-intensive. For SSD design, heavy communication between virtual platform and emulator has a negative impact on the performance of hybrid emulation. To minimize the communication overhead, the three-step partitioning method is newly proposed. The proposed method improves 12X SSD device initialization time compared to pure emulation.