Efficient Impedance Discontinuity Optimization Technique for High Speed Interfaces
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionThis paper introduces an efficient optimization technique to minimize impedance discontinuity caused by via and joint structure for high speed serdes interface. This method uses s-parameter extracted from pre-defined discontinuity structure of package design whose design parameters, such as via distance and clearance are varied, and evaluates discontinuity performance by calculating RILN. Proposed automated optimization flow can find the optimized design parameter without engineer's intervention and cover large number of cases to reach closest optimum solution in initial design phase.