DescriptionWith shrinkage of CMOS process technologies, VLSI design community has been observing a drift in design specifications based on layout design, and to achieve desire post layout simulation performance, both schematic and layout designer have to iterate multiple times. In current controlled Oscillator (CCO) circuit, the frequency is directly depending on capacitance and current flow in each inverter branch and It can be a recursive loop between considered capacitance in schematic vs post layout netlist. Means this could be a time-consuming process and involvement of multiple resources. However, this can be managed by re-using topologies, constraints used in similar architectural blocks. Currently existing tools do not fully support an approach where tool stores already silicon proven data in a file to reuse the same topography design. This paper talks about a method to completely automate a layout development flow based on already stored templates. This provides an opportunity to schematic designers to know the layout impacts on their design, so that designer can tune without involving layout designer and avoid schematic and layout iterations.