DescriptionDeveloping insights for problems produced by Static Timing Analysis (STA) and optimization for high performance microprocessor designs requires in-depth analysis of both timing and physical data; this is a big data problem. This task has four main challenges, including: managing design hierarchy, reporting, linking data across time, and providing a reliable and scalable platform. Our new system extends the Design Data (DD) model using a hybrid data store architecture and methodology. This system addresses the above challenges for circuit design analysis and debug.
The DD model efficiently stores read-only netlist, timing, power, and physical (e.g., placement, congestion, routing) data in a compressed binary file on disk. Furthermore, DD contains the full timing graph enabling efficient path traversal and custom interactive analysis. This binary file is extended with a timing path-based “hybrid cache data store” using an SQL database and custom DD WebSocket server.
Designers can generate metrics charts to evaluate progress and focus efforts over a project’s life cycle. They can compare past and current data sets to identify and assess specific design trends and failure modes. Designers can define custom rules to categorize, filter, triage, and assign timing paths which need to be fixed, even across multi-year projects.