Structural analysis for RDC with Set-Reset flop
TimeWednesday, December 8th5:00pm - 6:00pm PST
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionAbstract-Reset domain Crossing has emerged into a major and un-avoidable design step in modern ASIC design flows. In any Digital design, Reset Domain Crossing (RDC) is essentially a structure where a signal crosses over from one reset domain to another reset domain.
There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design structures where there are more than one asynchronous set/reset controlling a flop. Then there can be scenarios involving data transfer between two such flops. Another matter of concern is if the output of such flops is used as reset further down the design. In this case, the question arises if we should treat that as a new reset domain or should there be some strategy to reuse the priority information of the contributing resets or the should the set/reset values of the flop be considered or the usage of the generated reset.
We will try to look at the problem structurally and propose a strategy to reach a conclusion where we face such design structures.