Pioneering Low Power Modeling and Verification Technique for custom blocks
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionFPGA designs contain different kind of blocks. The Unified Power Intent (UPF) flow is streamlined for an ASIC block. However, power intent verification is not fully streamlined for pure custom and analog blocks. Custom blocks present challenges in netlisting flow, UPF coding, error counts in static checks and liberty modeling for the power related cells. For custom blocks, transistors need to be properly modeled in the netlist. UPF needs to be simplified and coded correctly. Power cells needs to be modeled correctly using liberty models. Results needs to be in a reasonable number for easy review. Hence, proper violation tags need to be chosen in a static verification tool. Custom blocks UPF flow needs to be modeled correctly, simple to use, scalable, easy to review. This will ensure that both ASIC and custom blocks can UPF standard with low power tools for their power intent definition and verification. Through this paper, a novel innovative approach for verifying custom blocks is presented.