Priority Synthesis in Physical Synthesis
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionPhysical Synthesis uses estimated relative timing criticality to prioritize critical regions during design timing closure. This also applies to dispensing limited precious resources available such as lower-vt, wider wires. However, it is possible that more-critical regions may be closed easily by logic redesign or more accurate boundary assertions while less-critical regions may not have such options and struggle. Such less-critical regions may need to be prioritized higher during Physical Synthesis. This is especially helpful earlier in the design cycle, to evaluate viability of design timing closure. Priority Synthesis feature is aimed at addressing this need.
This work focuses on significantly enhancing priority infrastructure and improving timing QOR. Highlights include infrastructure that allows identification of priority regions along with customization of precious resources earmarked exclusively for such regions. In addition, special optimization steps that target priority regions have been created. Among other things such steps ”steal” or redirect routing resource from non-priority regions to enhance priority regions, when appropriate. Based on early user feedback, the timing in priority regions for a challenging design in the field is almost closed with Priority synthesis feature potentially paving way for cycle time reduction. This concept is being currently extended to routing steps.