DescriptionParasitic and layout depended effect (LDE) are become more prominent for advanced node circuit. In this paper, we presented a novel graph neural network based post-layout parasitic estimation methodology which can accurately predict both routing and individual transistor parasitic based on pre layout schematics. The novelty of the approach is elaborated in the following: Graph based circuit reduction technique is developed to annotate full post layout extraction information into schematics level. We demonstrate pre layout annotated schematic estimation vs full extraction layout final delay time delta can be bounded by within ±5%. To maximize the information from schematic level design, three layers of attention and SAGE based hetero graph neural network is used. Contrast to previously reported graph neural network based parasitic estimation, our circuit graph nodes introduce dual feature vectors to predict parasitic of transistor and wire at the same time. Individual transistor gate, source and drain parasitic are trained and predicted separately. This will help future transfer learning between different technology nodes. The hetero GNN based machine learning model is applied in a most advanced process node and result error distribution are within +-5% for 3Sigma variations.