Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionIntroduction: Developments are consistently under schedule pressure with limited resources, leaving little room for surprises in development.

Current challenge: ASIC and FPGA developments become unpredictable due to challenges in functional verification. This uncertainty often results from lesser quality RTL code. Challenging debug and hard-to-find issues are caused by common mistakes in design and coding. While static and formal verification tools find these issues, problems ensue without consistent use and enforcement.

Proposed solution: Integrating static and formal verification tools into both the check-in and regression processes can augment functional verification, resulting in less uncertainty. The more integrated with the code repositories, the easier it should be to implement and enforce.

Our proposed solution integrates these tools into our automated GIT Continuous Integration flow, an example being the open-source GITLAB-CI. By implementing quality checks of increasing rigor to check-ins, nightly regressions, and weekly regressions, across integrated testing domains such as SystemVerilog random stimulus testing, code-coverage checking, static Lint, formal Lint and clock/reset domain crossing checks, we should see more predictable, efficient development.

Results: We observed the expected results with a minimum of effort due to the ease of using GITLAB-CI. Results will be available upon acceptance.