Preventing Gate-level Glitches on Clock-Domain Crossing Paths
TimeWednesday, December 8th5:00pm - 6:00pm PST
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionAs we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. At the gate-level, CDC paths are often prone to glitch defects that are introduced during the synthesis, design-for-test, design-for-safety and power optimization process. An increasing number of companies are deploying CDC verification at both the RTL and the gate-level. To identify potential glitches at the gate-level, we use an automatic formal-based glitch detection methodology. The methodology utilizes structural CDC analysis, expression analysis, and formal methods to prune and find real glitches in the design.
Previously, we have been focusing on preventing and catching glitches on data multiplexing paths. After deployed gate-level CDC on several projects, we learned that it is even more critical to verify glitches on the unsynchronized and combinational CDC paths.