Analog in memory computing optimization with TOPS/W Methodology
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionAnalog in-memory computing is attractive for low power AI application but the performance really depends on the co-optimization from system to material. In the early design phase, it is important to consider about the whole system performance with tradeoff among sub-circuits. We have proposed a simple methodology to quick evaluate the performance of the initial architecture and based on that to optimize the architecture, algorithm or circuit structure to improve the overall performance.