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Presentation

Early vectorless scan analysis for complex SOC
TimeWednesday, December 8th5:00pm - 6:00pm PST
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionAs we approach bleeding edge process nodes, the densities of transistors on integrated circuits has increased drastically. To manufacture defect free silicon while also reducing test time, scan architecture complexity has increased. This has resulted in high power during scan testing. Hence analysis of IR and current for scan patterns is critical. In traditional flow, scan current analysis is done on netlist based VCD simulation. For any design the netlist VCD analysis is too late in the cycle to provide feedback for any change in scan chain partitions. This paper describes scan vectorless analysis to detect and fix problems like IR, package feedback early in the design cycle. This flow also enables us to determine power integrity of scan architecture without waiting for scan vectors (VCD/FSDB).