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Presentation

Efficient High-Sigma Verification of Standard Cell Libraries
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionGiven the increasing complexity and variability of state-of-the-art process technologies, circuit functionality must be robust to ensure high chip yields. Arm Physical Design Group develops standard cell library products across various foundries and process technologies. Flip-flop cells within these libraries must have their functionality verified to ensure that internal failure mechanisms will not cause yield loss. Compute and turnaround time costs are too expensive when using brute force monte-carlo simulation to perform this verification at high-sigma functional yield. Siemens EDA has developed the Worst-Case Yield Solver (WCYS) flow as part of the Solido Variation Designer tool enabling Arm to verify flop functionality to 6-sigma yields and beyond. To further reduce compute and turnaround time costs, Arm runs the WCYS flow in the cloud. Arm and Siemens EDA are working to enable the WCYS flow on Arm architecture machines in the cloud to realize further compute cost savings compared to alternate CPU architectures.