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Presentation

Mitigating Variability Challenges of IPs for Robust Design
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionSTMicroelectronics provides a comprehensive set of digital IPs, including standard cells and memory IPs, for IoT, automotive, and artificial intelligence applications. Verifying the variability of these IPs is essential to achieve high silicon yield maintaining power, performance and area requirements for the target SoC. The verification of these IPs is complex and requires multi-dimensional flows as each IP has to be operational across multiple processes, voltage and temperature (PVT) conditions.

The brute force method of running Monte Carlo simulation across all PVTs requires a prohibitive number of simulations. SoC applications demand low ppm targets and thus requires high-sigma yield. This results in millions and billions of simulations. The traditional method of running a subset of brute force Monte Carlo simulation and extrapolating to the target sigma is not scalable. And it does not account for non-Gaussian behavior, hence being inaccurate.

We present how the challenges mentioned above are addressed, and high yield is achieved; using machine-learning enabled variation-aware design and verification techniques and tools, to verify and quantify variability in orders-of-magnitude fewer simulations, with an accuracy of a brute force technique. We illustrate the flow, resulting in optimal performing standard cells and memory IP designs with higher silicon yield.