DescriptionMost of the modern SOCs have significant complex analog and mixed signal content which is often developed and integrated as hard IPs (or hard macros) at the top-level. Depending on the nature of the SOC, there could be different strategies adopted for top-level integration of these hard IPs (DOT: Digital on Top, AOT: Analog on Top and MSOT: Mixed Signal on Top). It is important that IP integration is done carefully to take care of all the integration requirements with signoff checks (Timing, SI, noise, IR, power management, physical routing constraints & Reliability etc.). This requires various EDA models to be supported for hard IPs to enable faster integration & silicon quality through signoff analyses. Model requirement varies with IP integration style. Paper proposes an automated system for development and delivery of various EDA models with comprehensive quality checks. System generates all the required EDA models across different integration styles, thus making it independent of the integration style and enables reuse across multiple SOCs using different integration style. Comprehensive quality checks eliminate potential iterations between IP owners & SOC design team and ensure silicon quality. System has resulted in significant cycle time improvement with improved silicon quality for multiple products.