High Bandwidth All-Digital Clock and Data Recovery Architecture
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
DescriptionA fully digital, RTL-Synthesizable low area-power solution to recover serial data using a single phase Nyquist clock . The proposed architecture circumvents the contemporary phase detector and control loop techniques and obviates the need of multi-phase clocks. This mitigates the complexity of the clock distribution network and eliminates the need of a dedicated PLL as a source of clock phases. The proposed data recovery mechanism is a non-linear process without any feedback inertia and is immune to the effects of loop bandwidth. This enables the system to tolerate very high frequency jitter. The incoming serial data is recovered in a parallel format that is always synchronized with a low rate derivative of the system clock. Results demonstrate high frequency total jitter tolerance beyond 0.75UI and ppm immunity over 5000ppm