An automated decision-making tool to accelerate Computational SRAM design for memory-bound applications
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionComputational SRAM might be used as energy-efficient vector processing units by memory-bound ML/AI applications requiring intensive data flow between CPU and memories. We present a tool that draws on a wide range of SRAM compilers available in the target technology to select the most suitable SRAM type, configuration and instance size to respect the user specifications (instruction frequency, memory capacity...). Trade-off between power consumption and footprint of the memory can also be specified. Results show that Single-Port register files and SRAMs are still preferred except for large memory sizes and high instruction frequencies where Dual-Port SRAMs are more suitable.