Presentation
Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology
TimeWednesday, December 8th1:30pm - 3:00pm PST
Location2008
Event Type
Designer, IP and Embedded Systems Track Presentations
Presented In-Person
IP
Security
DescriptionAccording to the National Vulnerability Database, there has been an exponential growth in hardware vulnerabilities over the last few years. In this 90-minute session, we bring together several individuals from industry to discuss the important standards and initiatives working to address this growing problem including Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) and the hardware Common Weakness Enumeration (CWE). The session will include both presentations and live demos supporting the adoption of these important initiatives. The agenda is as follows:
• Intro to Accellera’s Security Annotation for Electronic Design Integration (SA-EDI)
• Presenter: Mike Borza (10mins)
• MITRE’s Hardware Common Weakness Enumerations
• Presenter: Jason Fung (15mins)
• Hardware Assurance Database and Sharing
• Presenter: Jeremy Bellay (15mins)
• Demonstrations that showcase the SA-EDI with Weakness Enumerations:
• OneSpin/Perforce
Presenters: John Hallman, Vishal Moondhra (30mins)
• Tortuga Logic
Presenter: Anders Nordstrom (20mins)
• Intro to Accellera’s Security Annotation for Electronic Design Integration (SA-EDI)
• Presenter: Mike Borza (10mins)
• MITRE’s Hardware Common Weakness Enumerations
• Presenter: Jason Fung (15mins)
• Hardware Assurance Database and Sharing
• Presenter: Jeremy Bellay (15mins)
• Demonstrations that showcase the SA-EDI with Weakness Enumerations:
• OneSpin/Perforce
Presenters: John Hallman, Vishal Moondhra (30mins)
• Tortuga Logic
Presenter: Anders Nordstrom (20mins)