Multi-core System Verification Using Uvm Portable Stimulus​
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionThe fast-moving technological innovations have created a huge pressure on silicon requirements which translates to more design complexity and shrinking time to market. To address the need for reduction in verification cycle for complex multi-core designs, a scalable and portable method has been proposed that alleviates the bottlenecks created by conventional C-based stimuli. Especially in a design containing multiple cores having a similar set of peripheral and platform IPs connected to them, the problem worsens in the conventional approach. The method thus proposed provides a Shift Left approach of creating portable stimuli to such complex multi-core designs.