Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionThis paper describes how Menta and Codasip enable customers to extend processors in systems on chip (SoC) after they have been manufactured.
The RISC-V ISA is modular and allows custom instructions. Codasip Studio can be used to extend a Codasip core using custom instructions with the necessary additional logic implemented in the datapath. The joint solution allows this extra logic to be implemented in the field using an eFPGA co-extended core.
Specialized user interface tools to program the eFPGA matrix and to set up the RISC-V application programmable parameters, will be provided within a complete and optimized software solution.