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Presentation

Andes ACE feature extended on Menta eFPGA for RISC-V cores ISA reconfigurability in the field
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionMenta and Andes are providing an extension of ACE software feature, in hardware, allowing to add or reconfigure any Instruction Set Architecture (ISA) in the field.
ACE is a powerful framework allowing Andes customers to set new instructions on the Andes RISC-V processor cores. The joint solution is the implementation of RISC-V ISA on eFPGA co-extended core.
The solution does not break any software compatibility and leaves space for development and differentiation. Specialized user interface tools to program the eFPGA matrix and to set up the RISC-V application programmable parameters, will be provided within a complete and optimized software solution.