Handling SoC Verification: Changing the Paradigm in Verification Approaches
TimeTuesday, December 7th3:00pm - 3:45pm PST
DAC Pavilion Panels
DescriptionModern SoC complexity is driving a new verification frontier. The verification of an SoC has always been a departure from the more standardized techniques employed in large block or sub-system, both in terms of test requirements as well as sheer complexity and size. However, new issues such as safety, security, processor instruction flexibility layered on top of advanced applications including 5G, AI, Quantum Computing, etc. have driven the need for different thinking.
Simulators, emulators and formal-based apps are essential tools in the verification teams’ armament. But what is the most effective way to augment the core capabilities to deliver these intensely complex chips on time? For example, do we invest in accelerating test content production through techniques such as Portable Stimulus. Or should the focus be on additional and advanced static verification methods.
Moderator Brian Bailey, technology editor/EDA for Semiconductor Engineering, will lead two well-known, senior engineers who are responsible for next generation verification flow development. They will consider and discuss next generation needs and the directions they can take. Two vendor CEOs will attempt to address those needs and explain why their method is the most effective use of time and budget.
Come and witness an animated and lively discussion as we watch an open and frank conversation, often held behind closed doors in many semiconductor and electronic systems companies.