Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?
TimeWednesday, December 8th2:00pm - 2:45pm PST
DAC Pavilion Panels
DescriptionThe tremendous advances in Integrated Circuit (IC) Design that have spawned amazing innovation have also increased the complexity of Design Verification (DV).
DV today takes up more than half the time and cost of designing an IC. Additionally, DV requires a significant amount of engineering talent, simply put, there just aren’t enough DV engineers being produced to meet this demand.
To address the future challenges of verification, DV engineers must reinvent themselves and evolve into the DV Engineer 2.0. In this panel we will debate if ML/AI and Software 2.0 – the move toward a more abstracted way of designing electronics chips and systems – will play a role in helping the Design and Verification Engineer 2.0 to take on the challenge of reducing the cost and time of design and verification, while challenging the traditional Software 1.0 stack. Our debate will include the following areas:
• Deep Neural Network (DNN) Models and Software 2.0
• Functional Verification and Coverage improvement using ML
• Formal Verification
• Language models
• Machine Learning Model Deployment in Production
• How EDA companies need to evolve to meet these new challengers
With the proliferation of Software 2.0 and Machine Learning, will the Design and Verification Engineer 2.0 be twice as productive as they are today? Will they acquire the skill sets to model complex algorithms using Machine Learning Models and challenge traditional software 1.0 from EDA companies? We’ll offer a multitude of expert perspectives.