Trust and verify. Overcoming costly and piecemeal approaches to pre-silicon side-channel attack vulnerability analysis and verification
TimeMonday, December 6th2:00pm - 2:45pm PST
DAC Pavilion Panels
DescriptionSide-channel vulnerabilities strike fear into the hearts of design engineers – as well as corporate lawyers and executives. But analyzing and uncovering potential vulnerabilities can be costly and time-consuming. Existing EDA tool flows aren’t adequate to meet the challenges, so analysis is typically performed after the first-silicon prototype tapeout. This requires expertise and can prompt expensive silicon re-spins. The clear and present danger of side channel attacks, and the lack of a robust EDA security analysis methodology are creating a critical need for dedicated physical attack simulation tools that can root out vulnerabilities before prototype.
Panelists will discuss the gaps and downsides of current and new tools as well as a path forward to timely, efficient, and thorough pre-silicon side-channel attack vulnerability analysis. How can you better secure your design without hampering your design schedule and cost? Bring your questions – it should be a lively discussion!