RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
TimeWednesday, December 8th2:35pm - 2:57pm PST
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
Digital Design, Timing and Simulation
DescriptionGate sizing for timing optimization is performed extensively throughout Electronic Design Automation (EDA) flows. However, existing algorithms in commercial tools heavily rely on meta-heuristics which lead to sub-optimal sizing solutions. Reinforcement Learning (RL) is a disruptive paradigm that achieves high-quality optimization results beyond traditional algorithms. In this paper, we formulate gate sizing as an RL process, and propose RL-Sizer, an autonomous gate sizing agent, which performs timing optimization in an unsupervised manner. Experimental results on 6 commercial designs in advanced technologies (5-16nm) demonstrate that RL-Sizer consistently outperforms the sizing methodologies of an industry-leading EDA tool in total negative slack reduction.