Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects
TimeWednesday, December 8th11:30am - 12:00pm PST
SoC, Heterogeneous, and Reconfigurable Architectures
DescriptionChiplet-based architecture is a promising approach to accommodate the modern deep neural network models with increasing compute and on-chip storage requirements. However, the latency and bandwidth limitations of inter-chiplet electrical wires may become the performance bottleneck and yield diminishing returns as the number of chiplets scale up. In this paper, we propose a reconfigurable photonic network on the silicon interposer to connect multiple chiplets. The proposed silicon photonic network can adapt to the unicast, multicast, and broadcast communications in deep learning inference, and provide better scalability as compared to other state-of-the-art electrical and photonic designs.